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| Keywords: TEM of silicon nanowire (5887830328).jpg In this transmission electron micrograph a silicon nanowire is shown surrounded by a stack of thin layers of material called dielectrics which store electrical charge NIST scientists determined the best arrangement for this dielectric stack for the optimal construction of silicon nanowire-based memory devices Color added to image See also http //www nist gov/pml/semiconductor/nanowire-052411 cfm www nist gov/pml/semiconductor/nanowire-052411 cfm Credit Bonevich/NIST Disclaimer Any mention of commercial products within NIST web pages is for information only; it does not imply recommendation or endorsement by NIST Use of NIST Information These World Wide Web pages are provided as a public service by the National Institute of Standards and Technology NIST With the exception of material marked as copyrighted information presented on these pages is considered public information and may be distributed or copied Use of appropriate byline/photo/image credits is requested https //www flickr com/photos/usnistgov/5887830328/ TEM of silicon nanowire 2011-05-17 17 05 https //www flickr com/people/63059536 N06 National Institute of Standards and Technology PD-USGov National Institute of Standards and Technology https //flickr com/photos/63059536 N06/5887830328 2016-09-07 02 35 15 United States Government Work Uncategorized 2016 October 26 | ||||
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